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        <h1 class="title">Java工程师要懂的硬件知识-CPU-1-基础</h1>
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        <h1 class="post-card-title">Java工程师要懂的硬件知识-CPU-1-基础</h1>
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            <time class="post-time" title="2019-03-19 11:49:06" datetime="2019-03-19T03:49:06.985Z" itemprop="datePublished">2019-03-19</time>

            
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            <p>本文将按照从整体到局部的顺序一步步深入介绍现代CPU的结构组成；然后再在CPU简化结构的基础上，根据指令执行的过程一步步的分析CPU的执行阶段，并着重介绍指令流水线、乱序执行和分支预测这些广泛应用的优化技术及这些优化造成的冒险(Hazards)；最后再通过一段Java代码去印证所介绍的内容，去体会Java中的<code>Mechanical Sympathy</code>。</p>
<h1 id="CPU分层架构"><a href="#CPU分层架构" class="headerlink" title="CPU分层架构"></a>CPU分层架构</h1><h2 id="基础硬件知识"><a href="#基础硬件知识" class="headerlink" title="基础硬件知识"></a>基础硬件知识</h2><p>一般认识中的CPU就是主板插槽上那个很多针脚的小方块。对于PC服务器常常会有“2U2路12核24线程”这样的描述，现在参照下面图片中的“戴尔 PowerEdge R730”来解读。</p>
<img src="/2016-2-20-a-hardware-view-for-java-cpu-1/1.png">
<p>“2U”指的是这台服务器在机架上占用2个U位置，也就是这台服务器个头有2个单位那么大；“2路”指的是主板上有两个CPU插槽可以插2个CPU实体；“12核”是针对其使用的E5-2620处理器，每颗拥有6个CPU内核，2路也就是12颗内核；另外因为<code>超线程</code>技术所以操作系统中我们可以看到24个CPU逻辑内核也就是24线程。</p>
<p>更近一步的去观察，去观察硬件的组织结构，如下图：</p>
<img src="/2016-2-20-a-hardware-view-for-java-cpu-1/2.png">
<p>图中有两颗CPU每颗CPU上挂载了4条DDR内存条作为各自的主存储，然后两颗CPU之间通过<code>QPI</code>总线连接，这就是<a href="http://blog.beanmr.com/2016/01/14/a-hardware-view-for-java-preface/">上一篇</a>中介绍的NUMA结构的实例。整个结构通过<code>QPI</code>总线与一颗叫做<code>Intel C600</code>的芯片连接，这颗芯片提供着<code>SAS</code>,<code>SATA</code>,<code>PCIe</code>,<code>DMI</code>,<code>USB</code>等IO接口的控制服务。</p>
<p>再进一步的走到CPU内部就是如下图所示的一片在硅晶上的电路，其实硅晶是面积远小于平时看到的CPU大小。硅晶电路板上的对外连接点会被用导线连接到引脚让，然后用绝缘塑料或者陶瓷进行打包保护，这就是我们常说的封装技术。感兴趣的可以去看一下Intel工厂之旅之类的纪录片有一个感性的理解。</p>
<img src="/2016-2-20-a-hardware-view-for-java-cpu-1/3.png">
<p>进一步观察CPU电路板，这颗CPU电路的可以由以下各个组件构成，这些组件在<a href="http://blog.beanmr.com/2016/01/14/a-hardware-view-for-java-preface/">上一篇</a>中都有介绍有兴趣的小伙伴可以回看一下。</p>
<img src="/2016-2-20-a-hardware-view-for-java-cpu-1/4.png">
<p>最后说一句E5系列的CPU的L3缓存从表面看是一个整体，其实在这次架构设计中Intel加入L3分块的优化设计。原理我们不深究在这里只是提醒一下这个优化的思路是不是跟NUMA有点像。</p>
<img src="/2016-2-20-a-hardware-view-for-java-cpu-1/5.png">
<h2 id="分层结构-指令集-微架构"><a href="#分层结构-指令集-微架构" class="headerlink" title="分层结构/指令集/微架构"></a>分层结构/指令集/微架构</h2><p>重新回归到抽象的CPU世界，CPU体系也不是一个整体结构而是跟我们Java经典三层架构一样是分层。</p>
<img src="/2016-2-20-a-hardware-view-for-java-cpu-1/6.png">
<p>首先最上层是指令集，大的分类有精简指令集(RISC)，比如MIPS、ARM、Power Architecture指令集；复杂指令集CISC，如最经典的x86/x86-64指令集。指令集约定了CPU能完成的一系列的动作，比如ADD加法指令、MOV传送指令等。有了这一些列的指令就支撑起来了一门编程语言也就是常说的汇编语言，因此同样基于x86汇编的程序我们可以运行于Intel的处理器上也可以运行于AMD的处理器上。指令集保证了软件的兼容性，这也就是为什么我国自主知识产权的处理器“龙芯”要去购买MIPS指令集的授权，软硬件系统是一个庞大的生态体系，而指令集就是这个体系中的纽带。</p>
<p>虽然“龙芯”使用的MIPS指令集，生产也是意法半导体（ST）来代工的；但是我们说它是有自主知识产权的，就是因为它有自己的“GS464E”微架构。微架构就是某个指令架构下的一种实现结构设计，同样的指令集有不同的微架构、每种微架构最终可以有不同的电路实现和电路配置也就有了不同的CPU型号产品。</p>
<p>指令集-&gt;微架构-&gt;硬件实现，这就是CPU体系的一个分层结构。作为一个Java工程师虽然不必要深入了解每个层次的细节，但是至少要在头脑中有这样的一个体系以便于形成自己的知识体系和问题处理能力。</p>

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